High-speed, Loadable 16-bit Binary Counter

ثبت نشده
چکیده

The AT6000 Series field programmable gate array (FPGA) lets the designer implement a fast synchronous, loadable 16-bit binary counter that operates at 70 MHz on and off chip under the worst commercial operating conditions. The use of prescaled logic to generate the carry-enable signals for each count bit allows faster operation than traditional carry-enable generation methods. The 16-bit counter is very compact, yet the inpu ts and ou tpu ts are read i l y accessible. Description

برای دانلود متن کامل این مقاله و بیش از 32 میلیون مقاله دیگر ابتدا ثبت نام کنید

ثبت نام

اگر عضو سایت هستید لطفا وارد حساب کاربری خود شوید

منابع مشابه

Compact, Loadable 16- and 32-bit Binary Counters

Figure 1 is a block diagram representation of the I/O and architecture for a 16 or 32-bit counter. Pin CLK is the clock signal, RST the reset signal, and LOAD the load data signal. CLK is a positive, edge-triggered synchronous signal, and LOAD is an active low, synchronous signal. Pins D0 through D15, 31 are the load data inputs, and pins Q0 through Q15, 31 are the count bits. Pin Ci is the car...

متن کامل

All-optical Binary Counter by Using T Flip-flop: an Implementation

ABSTRACT: All-optical T (Toggle) flip-flop with preset (PR) and clear (CLR) are basic building modules for the development of ultra-high speed all optical binary counter. In this paper, a non-linear material based alloptical switching mechanism is utilized here to realize the all-optical T flip-flop with PR and CLR. A composite slab of linear medium (LM) and non-linear medium (NLM) is used to d...

متن کامل

A 1.2-ns16×16-Bit Binary Multiplier Using High Speed Compressors

For higher order multiplications, a huge number of adders or compressors are to be used to perform the partial product addition. We have reduced the number of adders by introducing special kind of adders that are capable to add five/six/seven bits per decade. These adders are called compressors. Binary counter property has been merged with the compressor property to develop high order compresso...

متن کامل

Low Voltage Operation of a 16-bit Counter in 32 nm CMOS Technology

The binary counter is a fundamental unit of computer operation. The goal of this project is to lower the supply voltage and find the optimal supply voltage which provided less power

متن کامل

Counter 2 Counter n Counter 3 CMM Memory Counter 1 Data Bus Sout

A comparison between a bit-level and a conventional VLSI implementation of a binary neural network is presented. This network is based on Correlation Matrix Memory (CMM) that stores relationships between pairs of binary vectors. The bit-level architecture consists of an n m array of bit-level processors holding the storage and computation elements. The conventional CMM architecture consists of ...

متن کامل

ذخیره در منابع من


  با ذخیره ی این منبع در منابع من، دسترسی به آن را برای استفاده های بعدی آسان تر کنید

برای دانلود متن کامل این مقاله و بیش از 32 میلیون مقاله دیگر ابتدا ثبت نام کنید

ثبت نام

اگر عضو سایت هستید لطفا وارد حساب کاربری خود شوید

عنوان ژورنال:

دوره   شماره 

صفحات  -

تاریخ انتشار 1999